A well-known characteristic of planar PN junctions is the reduction of breakdown voltage compared to that of a plane junction of the same profile due to field concentration at the junction periphery where the diffused layer curves up to the surface. A number of methods such as diffused field relief rings, junction termination extensions and field plates have been employed to make the planar breakdown of the simple geometry more nearly approach the planar breakdown for the profile in question. While these methods do increase the breakdown voltage, they require substantial die area and precise control of the substrate doping. Typical examples of these prior art methods are illustrated in U.S. Pat. No. 3,909,119 to Wolley. This patent also shows the use of a low impurity concentration substrate with an increased impurity concentration region of a first conductivity type being buried below an optimum impurity concentration of an opposite conductivity type so as to produce the desired value of plane breakdown which is lower than the planar breakdown of the original substrate. Other examples of using this concept for diodes is illustrated in U.S. Pat. No. 3,484,308 to Lesk and U.S. Pat. No. 3,814,997 to Takahashi et al.
While these patents provide an improvement over prior art diodes, they do not address the problem of forming bipolar transistors in integrated circuits with all the contacts on the top surface. The prior art cited above are discrete devices which make contact to the bottom of the PN junction by the bottom of the substrate and, thus, does not address the problem of low contact resistance in combination with the improved plane breakdown voltages. Since they are designed for plane breakdown voltage optimization, they are not directed to reducing collector resistance with possible planar breakdown. Thus, there exists the need for an improved bipolar transistor having low collector series resistance and improved planar collector-to-base breakdown voltage.